The present invention relates to a testing apparatus and a testing method, which are adapted for testing the semiconductor devices formed on a semiconductor wafer (hereinafter referred to simply as a wafer). More specifically, the invention relates to a testing apparatus and a testing method, which are designed to execute both a reliability test and an electric characteristic test (e.g., a high-speed test, a low-speed test) with respect to semiconductor devices formed on the wafer. (The semiconductor devices will be referred to simply as chips.)
In the semiconductor test process, an electric characteristic test is carried out for each of the chips formed on a wafer. By this test, the chips are screened to select those chips that are not defective in their electric characteristics. Good chips selected by the screening are then packaged by use of a synthetic resin or ceramic material in the subsequent assembling process. A reliability test is executed with respect to the packaged chips.
In the reliability test, thermal stress and electric stress are applied to the packaged chips so as to check whether they have potential defects.
Those chips which are determined as defective in the reliability test are removed, and a final electric characteristic test is executed only for the chips that are determined as good. In this manner, good-quality products are shipped from the factory.
In recent years, more and more small-sized sophisticated electric appliances have been developed. In accordance with this trend, efforts are being made for the miniaturization and high integration of chips. In order to provide small-sized electric appliances, flip chip technology has been developed. In this technology, so-called bare chips (i.e., chips that are not packaged) are mounted on circuit boards, and the market for bare chips has been developed. Before bare chips are put on the market, a reliability test has to be executed for them by use of a burn-in test apparatus. This test should not be carried out for the bare chips individually since the bare chips have to be handled with special care. Under the circumstances, a technique for executing a burn-in test with respect to the chips formed on the wafer has been developed. Such a technique is disclosed in Jpn. Pat. Appln. KOKAI Publications No. 7-231019, No. 8-5666 and No. 8-340030, for example.
Where bare chips are subjected to a reliability test in the state where they are formed on the wafer, quality-guaranteed bare chips can be dealt with in units of one wafer. This is very convenient in trading the bare chips.
However, the test time required for testing highly-integrated multi-bit chips is inevitably long. In addition, the number of multiple dies to be tested is restricted. Accordingly, the throughput is degraded, and the cost needed for the test is increased. Another problem is that there are two kinds of tests that have to be executed, one being an electric characteristic test which is executed by use of a probing apparatus, and the other being a reliability test which is executed by use of a burn-in testing apparatus. Broadly speaking, the former electric characteristic test includes two kinds: a low-speed/long-term test and a high-speed/high-accuracy test. It is therefore necessary to prepare three kinds of testing apparatuses: one for the high-speed test, another for the low-speed test, and the remaining one for the reliability test. The cost needed for these testing apparatuses is one cause of an increase in the test cost. Where a number of testing apparatuses are employed, the time needed for the transfer of wafers between these testing apparatuses cannot be neglected, further degrading the throughput of the test.